
W320-04
Document #: 38-07010 Rev. *B
Page 3 of 18
Function Table
[1]
S2
1
1
1
1
0
0
0
0
Mid
Mid
Mid
Mid
S1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
66 MHz
100 MHz
200 MHz
133 MHz
66 MHz
100 MHz
200 MHz
133 MHz
Hi-Z
TCLK/2
Reserved
Reserved
3V66[0:1]
(MHz)
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66BUFF[0:2]/
3V66[2:4]
(MHz)
66IN
66IN
66IN
66IN
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
66IN/3V66_5
(MHz)
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz Input
66 MHz
66 MHz
66 MHz
66 MHz
Hi-Z
TCLK/4
Reserved
Reserved
PCI_F/PCI
(MHz)
66IN/2
66IN/2
66IN/2
66IN/2
33 MHz
33 MHz
33 MHz
33 MHz
Hi-Z
TCLK/8
Reserved
Reserved
REF0(MHz)
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Hi-Z
TCLK
Reserved
Reserved
USB/DOT
(MHz)
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Hi-Z
TCLK/2
Reserved
Reserved
Notes:
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
2, 3, 4
1, 5
7, 8, 5
–
–
Swing Select Functions
Mult0
Board Target Trace/Term Z
Reference R, IREF
=
V
DD
/(3*Rr)
Rr = 221 1%, IREF = 5.00 mA
Output Current
V
OH
@ Z
1.0V @ 50
0
50
I
OH
= 4*IREF
1
50
Rr = 475 1%, IREF = 2.32 mA
I
OH
= 6*IREF
0.7V @ 50
Clock Driver Impedances
Impedance
Buffer Name
V
DD
Range
Buffer Type
Min.
Typ.
Max.
CPU, CPU#
Type X1
50
REF
3.135
–
3.465
Type 5
12
30
55
PCI, 3V66, 66BUFF
3.135
–
3.465
Type 5
12
30
55
USB
3.135
–
3.465
Type 3A
12
30
60
DOT
3.135
–
3.465
Type 3B
12
30
60
Clock Enable Configuration
PWR_DWN#
0
1
1
1
1
CPU_STOP#
X
0
0
1
1
PCI_STOP#
X
0
1
0
1
CPU
IREF*2
ON
ON
ON
ON
CPU#
FLOAT
FLOAT
LOW
ON
ON
3V66
LOW
ON
ON
ON
ON
66BUFF
LOW
ON
ON
ON
ON
PCI_F
LOW
ON
ON
ON
ON
PCI
LOW
OFF
ON
OFF
ON
USB/DOT
LOW
ON
ON
ON
ON
VCOS/
OSC
OFF
ON
ON
ON
ON
Note:
1.
2.
3.
4.
5.
6.
7.
TCLK is a test clock driven in on the XTALIN input in test mode.
“
Normal
”
mode of operation
Range of reference frequency allowed is min. = 14.316, nom. = 14.31818 MHz, max. = 14.32 MHz.
Frequency accuracy of 48 MHz must be +167PPM to match USB default.
Mid. is defined a Voltage level between 1.0V and 1.8V for three-level input functionality. Low is below 0.8V. High is above 2.0V.
Required for DC output impedance verification.
These modes are to use the SAME internal dividers as the CPU = 200 MHz mode. The only change is to slow down the internal VCO to allow under clock
margining.