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參數資料
| 型號： | W29C102Q-70B |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | PROM |
| 英文描述： | 64K 16 CMOS FLASH MEMORY |
| 中文描述： | 64K X 16 FLASH 5V PROM, 70 ns, PDSO40 |
| 封裝： | 10 X 14 MM, TSOP-40 |
| 文件頁數： | 3/21頁 |
| 文件大小： | 205K |
| 代理商： | W29C102Q-70B |
W29C102
Publication Release Date: March 1998
- 3 -
Revision A3
FUNCTIONAL DESCRIPTION
Read Mode
The read operation of the W29C102 is controlled by CE and OE, both of which have to be low for
the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip
is de-selected and only standby power will be consumed. OE is the output control and is used to gate
data from the output pins. The data bus is in high impedance state when either CE or OE is high.
Refer to the timing waveforms for further details.
Page Write Mode
The W29C102 is programmed on a page basis. Every page contains 128 words of data. If a word of
data within a page is to be changed, data for the entire page must be loaded into the device. Any
word that is not loaded will be erased to "FFh" during programming of the page.
The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists
of two steps. Step 1 is the word-load cycle, in which the host writes to the page buffer of the device.
Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously
written into the memory array for non-volatile storage.
During the word-load cycle, the addresses are latched by the falling edge of either CE or WE,
whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs
first. If the host loads a second word into the page buffer within a word-load cycle time (T
BLC
) of 200
μ
S, after the initial word-load cycle, the W29C102 will stay in the page load cycle. Additional words
can then be loaded consecutively. The page load cycle will be terminated and the internal
programming cycle will start if no additional word is loaded into the page buffer. A
7
to A1
5
specify the
page address. All words that are loaded into the page buffer must have the same page address. A
0
to
A
6
specify the word address within the page. The words may be loaded in any order; sequential
loading is not required.
In the internal programming cycle, all data in the page buffers, i.e., 128 words of data, are written
simultaneously into the memory array. The typical programming time is 5 mS. The entire memory
array can be written in 2.6 seconds. Before the completion of the internal programming cycle, the host
is free to perform other tasks such as fetching data from other locations in the system to prepare to
write the next page.
Software-protected Data Write
The device provides a JEDEC-approved optional software-protected data write. Once this scheme is
enabled, any write operation requires a series of three-word program commands (with specific data to
a specific address) to be performed before the data load operation. The three-word load command
sequence begins the page load cycle, without which the write operation will not be activated. This
write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by
noise during system power-up and power-down.
The W29C102 is shipped with the software data protection enabled. To enable the software data
protection scheme, perform the three-word command cycle at the beginning of a page load cycle. The
device will then enter the software data protection mode, and any subsequent write operation must be
preceded by the three-word program command cycle. Once enabled, the software data protection will
remain enabled unless the disable commands are issued. A power transition will not reset the
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| W29C102T-70 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K 16 CMOS FLASH MEMORY |
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