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參數資料
| 型號： | W25Z040A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 128K×36bit Pipeline ZWS(Zero-Wait-State) SRAM(128K×36位無等待時間的管線CMOS同步靜態RAM) |
| 中文描述： | 128K的× 36bit管道ZWS（零等待狀態）的SRAM（128K的× 36位無等待時間的管線的CMOS同步靜態內存） |
| 文件頁數： | 3/16頁 |
| 文件大小： | 136K |
| 代理商： | W25Z040A |
W25Z040A
Publication Release Date: April 1999
- 3 -
Revision A2
PIN DESCRIPTION
SYMBOL
TYPE
DESCRIPTION
A0
A16
I/O1
I/O36
CLK
Input, Synchronous
Host Address
I/O, Synchronous
Data Inputs/Outputs
Input, Clock
Processor Host Bus Clock
CLKE
Input, Synchronous
Clock Enable
CE1
, CE2,
CE3
Input, Synchronous
Chip Enables
WE
Input, Synchronous
Write Enable from System Controller
BW1
BW4
Input, Synchronous
Host Bus Byte Enables used with
WE
OE
Input, Asynchronous
Output Enable Input
ADV/LD
Input, Synchronous
Internal Burst Address Counter Advance(Sampled
High) / Load External Address (Sampled Low)
ZZ
Input, Asynchronous
Snooze Pin for Low-power State, internally pulled low
FT
Input, Static
This pin should be connected to V
DD
or unconnected
to meet the specification in pipelined mode operation.
LBO
Input, Static
Lower Address Burst Order
Connected to V
SS
: Device operates in linear mode.
Connected to V
DD
or unconnected: Device is in non-
linear mode.
V
DDQ
I/O Power Supply
V
SSQ
I/O Ground
V
DD
Power Supply
V
SS
Ground
RSV
Reserved Pin, Don't Use These Pins
NC
No Connection
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