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參數資料
| 型號： | W25P243A |
| 廠商： | WINBOND ELECTRONICS CORP |
| 英文描述： | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 64K的爆流水線× 64高速CMOS靜態RAM |
| 文件頁數： | 4/18頁 |
| 文件大小： | 264K |
| 代理商： | W25P243A |
W25P243A
- 4 -
FUNCTIONAL DESCRIPTION
The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel
systems (Interleaved mode) and linear
mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC
and the burst counter is incremented whenever ADV is sampled low.
BURST ADDRESS SEQUENCE
INTEL SYSTEM (LBO = V
DD
)
A[1:0]
A[1:0]
00
01
01
00
10
11
11
10
LINEAR MODE (LBO = V
SS
)
A[1:0]
A[1:0]
00
01
01
10
10
11
11
00
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
External Start Address
Second Address
Third Address
Fourth Address
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE[7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
ADDRESS
USED
CE1
CE2
CE3
ADSP
ADSC
ADV
OE
DATA
WRITE*
Unselected
No
1
X
X
X
0
X
X
Hi-Z
X
Unselected
No
0
X
1
0
X
X
X
Hi-Z
X
Unselected
No
0
0
X
0
X
X
X
Hi-Z
X
Unselected
No
0
X
1
1
0
X
X
Hi-Z
X
Unselected
No
0
0
X
1
0
X
X
Hi-Z
X
Begin Read
External
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
X
X
X
1
1
0
0
D-Out
Read
Continue Read
Next
1
X
X
X
1
0
1
Hi-Z
Read
Continue Read
Next
1
X
X
X
1
0
0
D-Out
Read
Suspend Read
Current
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
X
X
X
1
1
1
0
D-Out
Read
Suspend Read
Current
1
X
X
X
1
1
1
Hi-Z
Read
Suspend Read
Current
1
X
X
X
1
1
0
D-Out
Read
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|---|---|
| W25P243A-4A | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-5 | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-6 | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243AD-4A | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1.2V-vf 150ns 5uA-ir DO-41 5K/REEL-13 |
| W25P243AD-5 | RECTIFIER FAST-RECOVERY SINGLE 1.5A 100V 50A-ifsm 1.2V-vf 150ns 5uA-ir DO-15 5K/REEL-13 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| W25P243A-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243A-6 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243AD-4A | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| W25P243AD-5 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
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