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參數資料
| 型號： | REJ03F0059_M61533FP |
| 廠商： | Hitachi,Ltd. |
| 英文描述： | LEAD FREE EXT TEMP A6841 SOIC-20 |
| 中文描述： | 4通道電子音量帶AGC |
| 文件頁數： | 5/13頁 |
| 文件大小： | 374K |
| 代理商： | REJ03F0059_M61533FP |
M61533FP
Rev.1.0, Sep.19.2003, page 5 of 12
Relationship Between Data and Clock
D0
D1
D2
D3
D13
D14
D15
CLOCK
DATA
Data signal is read at the rising edge of CLOCK.
Make "H" at the timing which
DATA of D0-D15 make latch.
When DATA is "H", latch signal is
created at the falling edge of CLOCK.
Clock and Data Timings
tWHC
t
cr
25%
75%
LATCH
tWLC
tf
tr
tHLD tSHD
tHHD
tSLD
tHLD
(D0
D15)
tSLD
CLOCK
DATA
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