
OP490
REV. B
–11–
Figure 4. High Output Amplifier
HIGH OUT PUT AMPLIFIE R
T he amplifier shown in Figure 4 is capable of driving 25 V p-p
into a 1 k
load. Design of the amplifier is based on a bridge
configuration. A amplifies the input signal and drives the load
with the help of B. Amplifier C is a unity-gain inverter which
drives the load with help from D. Gain of the high output am-
plifier with the component values shown is 10, but can easily be
changed by varying R1 or R2.
SINGLE -SUPPLY MICROPOWE R QUAD
PROGRAMMABLE GAIN AMPLIFIE R
T he combination of quad OP490 and the DAC8408 quad 8-bit
CMOS DAC, creates a quad programmable-gain amplifier with
a quiescent supply drain of only 140
μ
A. T he digital code
present at the DAC, which is easily set by a microprocessor, de-
termines the ratio between the fixed DAC feedback resistor and
the resistance of the DAC ladder presents to the op amp feed-
back loop. Gain of each amplifier is:
V
OUT
V
IN
=
±256
n
where
n
equals the decimal equivalent of the 8-bit digital code
present at the DAC. If the digital code present at the DAC con-
sists of all zeros, the feedback loop will be open causing the op
amp output to saturate. T he 10 M
resistors placed in parallel
with the DAC feedback loop eliminates this problem with a very
small reduction in gain accuracy. T he 2.5 V reference biases the
amplifiers to the center of the linear region providing maximum
output swing.