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參數(shù)資料
| 型號： | MN6153UC |
| 廠商： | PANASONIC CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLL LSI with Built-In Prescaler |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 60 MHz, PDSO16 |
| 封裝： | 0.225 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 52K |
| 代理商： | MN6153UC |
For Communications Equipment
MN6153UC
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
(2) Comparating side
Notes
1.*1:
Preceding the input of the frequency dividing data for the comparating side, input test data consisting of
three "L" level bits to produce normal operation. Never use any other pattern.
2.
When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3.
When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4.
Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2
control bits)
5.
Drive the LE pin at "L" level while writing the data.
6.
"H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
7.
Writes are possible when the PS pin is either "H" or "L" level.
8.
Input the data MSB first.
9.
The data are inputted at the rising edge of the CLK signal.
CLK
DATA
LE
CLK
DATA
LE
1
2
3
4
5
21
22
23
17-bit frequency dividing data
1 bit
1 bit
1 bit
1 bit
"L"
"L"
Control bits
Control bits
Data input direction
Data input direction
MSB
LSB
Frequencey
dividing stage selection
"L" level
Frequencey
dividing stage selection
"H" level
Write selection
"H" level
Write selection
"H" level
1
2
17
18
19
MSB
LSB
3-bit test data
18-bit frequency dividing data
*1
3 bits "L" level
MSB
LSB
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