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參數資料
| 型號： | MM54HCT574WM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | TRI-STATE? Octal D-Type Latch / TRI-STATE Octal D-Type Flip-Flop |
| 中文描述： | HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 文件頁數： | 3/6頁 |
| 文件大?。?/td> | 127K |
| 代理商： | MM54HCT574WM |
AC Electrical Characteristics
MM54HCT573/MM74HCT573
V
CC
e
5.0V, t
r
e
t
f
e
6 ns T
A
e
25
§
C (unless otherwise specified)
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PHL
, t
PLH
Maximum Propagation Delay
Data to Output
C
L
e
45 pF
17
27
ns
t
PHL
, t
PLH
Maximum Propagation Delay
Latch Enable to Output
C
L
e
45 pF
16
27
ns
t
PZH
, t
PZL
Maximum Enable Propagation Delay
Control to Output
C
L
e
45 pF
R
L
e
1 k
X
C
L
e
5 pF
R
L
e
1 k
X
21
30
ns
t
PHZ
, t
PLZ
Maximum Disable Propagation Delay
Control to Output
14
23
ns
t
W
t
S
t
H
Minimum Clock Pulse Width
15
ns
Minimum Setup Time Data to Clock
5
ns
Minimum Hold Time Clock to Data
12
ns
AC Electrical Characteristics
MM54HCT573/MM74HCT573
V
CC
e
5.0V
g
10%, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HCT
54HCT
Symbol
Parameter
Conditions
T
A
eb
40 to 85
§
C
T
A
eb
55 to 125
§
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
Delay Data to Output
C
L
e
50 pF
18
30
38
45
ns
t
PHL
, t
PLH
Maximum Propagation Delay
Latch Enable to Output
C
L
e
50 pF
17
30
44
53
ns
t
PZH
, t
PZL
Maximum Enable Propagation
Delay Control to Output
C
L
e
50 pF
R
L
e
1 k
X
C
L
e
50 pF
R
L
e
1 k
X
C
L
e
50 pF
22
30
38
45
ns
t
PHZ
, t
PLZ
Maximum Disable Propagation
Delay Control to Output
15
30
38
45
ns
t
THL
, t
TLH
t
W
t
S
t
H
C
IN
C
OUT
C
PD
Maximum Output Rise and Fall Time
6
12
15
18
ns
Minimum Clock Pulse Width
15
20
24
ns
Minimum Setup Time Data to Clock
b
3
5
6
8
ns
Minimum Hold Time Clock to Data
4
12
15
18
ns
Maximum Input Capacitance
10
10
10
pF
Maximum Output Capacitance
20
20
20
pF
Power Dissipation Capacitance (Note 5)
OC
e
V
CC
OC
e
GND
5
52
pF
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
Truth Table
’HCT573
Output
Control
LE
Data
Output
L
L
L
H
H
H
L
X
H
L
X
X
H
L
Q
0
Z
H
e
high level, L
e
low level
Q
0
e
level of output before steady-state input conditions
were established.
Z
e
high impedance
’HCT574
Output
Control
Clock
Data
Output
L
L
L
H
u
u
L
X
H
L
X
X
H
L
Q
0
Z
H
e
High Level, L
e
Low Level
X
e
Don’t Care
u
e
Transition from low-to-high
Z
e
High impedance state
Q
0
e
The level of the output before steady state input conditions
were established.
3
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PDF描述 |
|---|---|
| MM54HCT643 | Inverting Octal TRI-STATE Transceiver |
| MM54HCT640 | Inverting Octal TRI-STATE Transceiver |
| MM54HCT640J | Inverting Octal TRI-STATE Transceiver |
| MM54HCT643J | Inverting Octal TRI-STATE Transceiver |
| MM74HCT640 | Inverting Octal TRI-STATE Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MM54HCT640 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT640J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT643 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT643J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT688 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Magnitude Comparator (Equality Detector) |
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