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CHAPTER 14 UART/SIO
Table 14.4-3 Functions of Each Bit in Serial Status and Data Register (SSD)
Bit name
Function
Bit 7
PER:
Parity error flag
This bit is set if a parity error occurs during reception and
is cleared when "0" is written to the RERC bit in the SMC2
register. When this flag is set, the data in SIDR becomes
invalid. If the PER bit is set when the RIE bit is set to "1,"
an interrupt occurs.
Bit 6
OVE:
Overrun error flag
This bit is set if an overrun error occurs during reception
and is cleared when "0" is written to the RERC bit in the
SMC2 register. When this flag is set, the data in SIDR
becomes invalid. If the OVE bit is set when the RIE bit is
set to "1," an interrupt occurs.
Bit 5
FER:
Framing error flag
This bit is set if an framing error occurs during reception
and is cleared when "0" is written to the RERC bit in the
SMC2 register. When this flag is set, the data in SIDR
becomes invalid. If the FER bit is set when the RIE bit is
set to "1," an interrupt occurs.
Bit 4
RDRF:
Received data register full
This bit is a flag indicating the state of the received data
register (SIDR). This bit is set when the received data is
loaded to the SIDR register and is cleared when the SIDR
register is read. If the RDRF bit is set when the RIE bit is
set to "1," an interrupt occurs.
Bit 3
TDRE:
Transmission data register
empty
This bit is a flag indicating the state of the serial
transmission data register (SODR). This bit is cleared
when the transmission data is written to the SODR
register and is set when the data is loaded to the shifter
for transmission and transmission of the data starts. If the
TDRE bit is set, an interrupt occurs.
Bit2
Bit1
Bit0
Unused bits
The read value is undefined.
Writing has no effect on operation.