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FM24C32U Rev. A.1
F
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Master
Transmitter/
Receiver
V
CC
V
CC
Typical System Configuration
Note:
Due to open drain configuration of SDA and SCL, a bus-level pull-up resistor is called for, (typical value = 4.7k
)
SDA
SCL
STOP
CONDITION
START
CONDITION
WORD n
8th BIT
ACK
tWR
Write Cycle Timing
Note:
The write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.