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參數資料
型號: AD9937KCPRL
廠商: ANALOG DEVICES INC
元件分類: 消費家電
英文描述: TVPS00RF-25-35PB W/ PC CONTACT
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC56
封裝: MO-220-VLLD-2, LFCSP-56
文件頁數: 26/44頁
文件大小: 410K
代理商: AD9937KCPRL
REV. 0
–26–
AD9937
VD
11-BIT
VD COUNTER
H1(A–D)
HMASK
1
2
3
H1(A–D)
H1(A, B)
PROGRAMMABLE CLOCK POSITIONS
1. HMASKSTART (PROGRAMMABLE AT MODE_REG(12))
2. HMASKSTOP (PROGRAMMABLE AT MODE_REG(12))
3. H1MASKPOL (PROGRAMMABLE AT MODE_REG(12))
THE POLARITY OF H1(A–D) DURING BLANKING IS PROGRAMMABLE
(H2(A, B) IS ALWAYS THE OPPOSITE POLARITY OF H1 (A–D))
Figure 18. Programmable Clock Positions for HMASK
Table XI. PBLK Registers
Length
(Bits)
Register
Type
Register Name
Range
Description
PBLK_LEVEL
1
Control 0x03
HIGH/LOW
0 = Blank Output Data to Zero,
1 = Blank Output Data to REFBLACK
Sets PBLK Toggle Position 1 within the Line
Sets PBLK Toggle Position 2 within the Line
Sets PBLK Toggle Position 3 within the Line
Sets PBLK Toggle Position 4 within the Line
Sets the Line Number the PBLK Pulse Will Start In
Sets the Line Number the PBLK Pulse Will Stop In
PBLKTOG1
PBLKTOG2
PBLKTOG3
PBLKTOG4
PBLKSTART
PBLKSTOP
12
12
12
12
11
11
Mode_Reg(9)
Mode_Reg(9)
Mode_Reg(10)
Mode_Reg(10)
Mode_Reg(11)
Mode_Reg(11)
0
4095 Pixel Locations
0
4095 Pixel Locations
0
4095 Pixel Locations
0
4095 Pixel Locations
0
2047 Line Number
0
2047 Line Number
001
002
003
000
000
11-BIT
VD COUNTER
VD
001
HD
HDLENx
*
HDLASTLEN
1
2
3
4
5
6
PROGRAMMABLE CLOCK POSITIONS
1. VDHD_INVERT (PROGRAMMABLE AT CONTROL 0x04)
2. VDTOG1 (PROGRAMMABLE AT MODE_REG(4))
3. VDTOG2 (PROGRAMMABLE AT MODE_REG(4))
4. HDTOG1 (PROGRAMMABLE AT MODE_REG(2))
OPTIONAL SECOND HD PULSE PER LINE
5. HDTOG2 (PROGRAMMABLE AT MODE_REG(2))
6. HDTOG3 (PROGRAMMABLE AT MODE_REG(3))
7. HDTOG4 (PROGRAMMABLE AT MODE_REG(3))
N – 1
*
X = 0, 1, 2, 3, 4 REPRESENTING CCD REGIONS
VDLEN
N 2048
7
12-BIT
HD COUNTER
Figure 17. VD and HD Programmable Locations
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