
AD9929
DIGITAL SPECIFICATIONS
Table 2. RGVDD = HVDD = 2.7 V to 3.6 V, DVDD = DRVDD = 2.7 V to 3.6 V, C
L
= 20 pF, T
MIN
to T
MAX
, unless otherwise noted.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS (Except H and RG)
High Level Output Voltage @ I
OH
= 2 mA
Low Level Output Voltage @ I
OL
= 2 mA
RG and H-DRIVER OUTPUTS (H1 to H2)
High Level Output Voltage @ Max Current
Low Level Output Voltage @ Max Current
RG Maximum Output Current (Programmable)
H1 and H2 Maximum Output Current (Programmable)
Maximum Load Capacitance
ANALOG SPECIFICATIONS
Table 3. AVDD = 3.0 V, f
CLI
= 36 MHz, T
MIN
to T
MAX
, unless otherwise noted.
Parameter
Min
Typ
CDS
Allowable CCD Reset Transient
500
Max Input Range before Saturation
1.0
Max CCD Black Pixel Amplitude
±100
VARIABLE GAIN AMPLIFIER (VGA)
Max Output Range
2.0
Gain Control Resolution
1024
Gain Monotonicity
Guaranteed
Gain Range
Low Gain
6
Max Gain
40
BLACK LEVEL CLAMP
Clamp Level Resolution
255
Clamp Level
Min Clamp Level
0
Max Clamp Level
255
A/D CONVERTER
Resolution
10
Differential Nonlinearity (DNL)
±0.5
No Missing Codes
Guaranteed
Full-Scale Input Voltage
2.0
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
2.0
Reference Bottom Voltage (REFB)
1.0
SYSTEM PERFORMANCE
Gain Accuracy
Low Gain (VGA Code = 22)
6
Max Gain (VGA Code = 994)
40
Peak Nonlinearity, 500 mV Input Signal
0.1
Total Output Noise
0.3
Power Supply Rejection (PSR)
40
Rev. A | Page 4 of 64
Symbol
V
IH
V
IL
I
IH
I
IL
C
IN
V
OH
V
OL
V
OH
V
OL
Min
2.1
2.2
VDD 0.5
100
Typ
10
10
10
Max
0.6
0.5
0.5
15
30
Unit
V
V
μA
μA
pF
V
V
V
V
mA
mA
pF
Max
Unit
mV
V p–p
mV
V p–p
Steps
dB
dB
Steps
LSB
LSB
LSB
Bits
LSB
V
V
V
dB
dB
%
LSB rms
dB
Notes
See input signal characteristics in Table 1.
LSB measured at ADC output.
Includes entire signal chain.
Gain = (0.035 × Code) + 5.2 dB.
12 dB gain applied.
AC grounded input, 6 dB gain applied.
Measured with step change on supply.