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參數資料
| 型號： | AD9923ABBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 17/88頁 |
| 文件大小： | 852K |
| 代理商： | AD9923ABBCZRL |
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AD9923A
Rev. 0 | Page 17 of 88
NOTES
1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.
2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS.
3. OUTPUT DELAY (
t
OD
) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE.
P[0]
P[48] = P[0]
PIXEL
PERIOD
P[12]
P[24]
P[36]
DOUT
DCLK
t
OD
0
Figure 21. Digital Output Phase Adjustment
DCLK
D[0:11]
CCDIN
CLI
SHD
(INTERNAL)
N
N+1
N+2
N+15
N+14
N+13
N+12
N+8
N+7
N+6
N+5
N+4
N+3
N+16
N–14
N–4
N–5
N–6
N–7
N–8
N–9
N–10
N–11
N–12
N–13
N–3
N–2
N
N–1
SAMPLE PIXEL N
t
CLIDLY
t
DOUTINH
N–17
N–4
N–8
N–9
N–10
N–11
N–12
N–13
N–14
N–15
N–16
N–3
N–2
N
N–1
ADC DOUT
(INTERNAL)
N+11
N+10
N+9
N–7
N–6
N–5
N–17
N–15
N–16
N+17
NOTES
1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT WITH RESPECT TO CLI LOCATION.
3. INHIBIT TIME FOR DOUT PHASE IS DEFINED BY
t
, WHICH IS EQUAL TO SHDLOC PLUS 11 EDGES. IT IS RECOMMENDED THAT
THE 12 EDGE LOCATIONS FOLLOWING SHDLOC NOT BE USED FOR THE DOUTPHASE LOCATION.
4. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE THE SHPLOC EDGE OR THE 11 EDGES FOLLOWING SHPLOC.
5. RECOMMENDED VALUE FOR
t
(DOUT DLY) IS 4ns.
6. THE DOUT LATCH CAN BE BYPASSED USING REGISTER 0x01, BIT [1] = 1 SO THAT THE ADC DATA OUTPUTS APPEAR DIRECTLY AT
THE DATA OUTPUT PINS. THIS CONFIGURATION IS RECOMMENDED IF THE ADJUSTABLE DOUT PHASE IS NOT REQUIRED.
PIPELINE LATENCY = 16 CYCLES
0
Figure 22. Digital Data Output Pipeline Delay
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