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參數資料
| 型號： | AD9822 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete 14-Bit CCD/CIS Signal Processor |
| 中文描述： | 完整的14位防治荒漠化公約/ CIS信號處理器 |
| 文件頁數： | 13/15頁 |
| 文件大小： | 150K |
| 代理商： | AD9822 |
REV. A
–13–
AD9822
Figure 12 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal will be restored to “zero.” After the large dc
offset is removed, the signal can be scaled using the PGA to
maximize the ADC’s dynamic range.
AD9822
OFFSET
RED-OFFSET
GREEN-OFFSET
BLUE-OFFSET
VINR
VING
VINB
RED
GREEN
BLUE
0.1
m
F
AVDD
VREF FROM
CIS MODULE
DC OFFSET
R1
R2
SHA
SHA
SHA
Figure 12. SHA-Mode Used with External DC Offset
Programmable Gain Amplifiers
The AD9822 uses one Programmable Gain Amplifier (PGA) for
each channel. Each PGA has a gain range from 1x (0 dB) to
5.8x (15.5 dB), adjustable in 64 steps. Figure 6 shows the PGA
gain as a function of the PGA register code. Although the gain
curve is approximately “linear in dB”, the gain in V/V varies
nonlinearly with register code, following the equation:
Gain
G
=
+
5 7
.
1
4 7
.
63
63
where
G
is the decimal value of the gain register contents, and
varies from 0 to 63.
PGA REGISTER VALUE – Decimal
15
0
G
12
9
6
3
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 6063
5.7
5.0
4.0
3.0
2.0
1.0
G
Figure 13. PGA Gain Transfer Function
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9822-EB | 制造商:Analog Devices 功能描述: |
| AD9822JR | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W |
| AD9822JRRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:14 BIT AFE WITH 12 BIT LINEARITY - Bulk |
| AD9822JRS | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SSOP |
| AD9822JRSRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 14-Bit 5V 28-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:14 BIT AFE WITH 12 BIT LINEARITY - Bulk |
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