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參數資料
| 型號： | AD9281 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Channel 8-Bit Resolution CMOS ADC |
| 中文描述： | 雙通道8位分辨率的CMOS模數轉換器 |
| 文件頁數： | 12/19頁 |
| 文件大小： | 406K |
| 代理商： | AD9281 |
AD9281
–12–
REV. E
SELECT
When the select pin is held LOW, the output word will present
the “Q” level. When the select pin is held HIGH, the “I” level
will be presented to the output word (see Figure 1).
The AD9281’s select and clock pins may be driven by a com-
mon signal source. The data will change in 5 ns to 11 ns after
the edges of the input pulse. The user must make sure the inter-
face latches have sufficient hold time for the AD9281’s delays
(see Figure 28).
CLOCK
DATA
I LATCH
CLOCK
DATA
Q LATCH
CLK
DATA
OUT
SELECT
I
PROCESSING
Q
PROCESSING
CLOCK
SOURCE
Figure 28. Typical De-Mux Connection
APPLICATIONS
USING THE AD9281 FOR QAM DEMODULATION
QAM is one of the most widely used digital modulation schemes in
digital communication systems. This modulation technique
can be found in both FDMA as well as spread spectrum (i.e.,
CDMA) based systems. A QAM signal is a carrier frequency
which is both modulated in amplitude (i.e., AM modulation)
and in phase (i.e., PM modulation). At the transmitter, it can
be generated by independently modulating two carriers of iden-
tical frequency but with a 90
°
phase difference. This results in
an inphase (I) carrier component and a quadrature (Q) carrier
component at a 90
°
phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier or IF frequency. Figure 29 shows
a typical analog implementation of a QAM modulator using a
dual 10-bit DAC with 2
×
interpolation, the AD9761. A QAM
signal can also be synthesized in the digital domain thus requir-
ing a single DAC to reconstruct the QAM signal. The AD9853
is an example of a complete (i.e., DAC included) digital QAM
modulator.
0
90
DSP
OR
ASIC
10
CARRIER
FREQUENCY
NYQUIST
FILTERS
TO
MIXER
QUADRATURE
MODULATOR
AD9761
IOUT
QOUT
Figure 29. Typical Analog QAM Modulator Architecture
DIGITAL INPUTS AND OUTPUTS
Each of the AD9281 digital control inputs, CHIP SELECT,
CLOCK, SELECT and SLEEP are referenced to AVDD and
AVSS. Switching thresholds will be AVDD/2.
The format of the digital output is straight binary. A low power
mode feature is provided such that for STBY = HIGH and the
clock disabled, the static power of the AD9281 will drop below
22 mW.
CLOCK INPUT
The AD9281 clock input is internally buffered with an inverter
powered from the AVDD pin. This feature allows the AD9281
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.
The pipelined architecture of the AD9281 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the logic family recommended to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 28 MSPS
operation. Running the part at slightly faster clock rates may be
possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9281 at slower clock rates.
The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.
DIGITAL OUTPUTS
Each of the on-chip buffers for the AD9281 output bits (D0–D9)
is powered from the DVDD supply pin, separate from AVDD.
The output drivers are sized to handle a variety of logic families
while minimizing the amount of glitch energy generated. In all
cases, a fan-out of one is recommended to keep the capacitive
load on the output data bits below the specified 20 pF level.
For DVDD = 5 V, the AD9281 output signal swing is compat-
ible with both high speed CMOS and TTL logic families. For
TTL, the AD9281 on-chip, output drivers were designed to
support several of the high speed TTL families (F, AS, S). For
applications where the clock rate is below 28 MSPS, other TTL
families may be appropriate. For interfacing with lower voltage
CMOS logic, the AD9281 sustains 28 MSPS operation with
DVDD = 3 V. In all cases, check your logic family data sheets
for compatibility with the AD9281’s Specification table.
A 2 ns reduction in output delays can be achieved by limiting
the logic load to 5 pF per output line.
THREE-STATE OUTPUTS
The digital outputs of the AD9281 can be placed in a high
impedance state by setting the CHIP SELECT pin to HIGH.
This feature is provided to facilitate in-circuit testing or evaluation.
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