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參數資料
| 型號： | AD808-622BRRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字傳輸電路 |
| 英文描述： | Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming |
| 中文描述： | RECEIVER, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁數： | 2/12頁 |
| 文件大小： | 145K |
| 代理商： | AD808-622BRRL |
AD808–SPECIFICATIONS
Parameter
QUANT IZER–DC CHARACT ERIST ICS
Input Voltage Range
Input Sensitivity, V
SENSE
Input Overdrive, V
OD
Input Offset Voltage
Input Current
Input RMS Noise
Input Peak-to-Peak Noise
QUANT IZER–AC CHARACT ERIST ICS
Upper –3 dB Bandwidth
Input Resistance
Input Capacitance
Pulsewidth Distortion
LEVEL DET ECT
Level Detect Range
REV. 0
–2–
Condition
Min
T yp
Max
Units
@ P
IN
or N
IN
P
IN
–N
IN
, Figure 1, BER =
≤
1
×
10
–10
Figure 1, BER =
≤
1
×
10
–10
2.5
10
5
V
S
V
mV
mV
mV
μ
A
μ
V
mV
4.0
2.0
1.0
10
100
1.5
BER =
≤
1
×
10
–10
BER =
≤
1
×
10
–10
600
800
10
2
50
MHz
k
pF
ps
R
T HRESH
= 22.1 k
R
T HRESH
= 6.98 k
R
T HRESH
= 0
DC Coupled
R
T HRESH
= 22.1 k
(See Figure 8)
R
T HRESH
= 6.98 k
R
T HRESH
= 0
Load = +3.2 mA
Load = –3.2 mA
6.5
13
28.5
0.1
10
18
40
13.5
23
45.5
1.5
9.0
9.0
10.0
mV
mV
mV
μ
s
dB
dB
dB
V
V
Response T ime
Hysteresis (Electrical)
5
5.1
7.0
4.7
0.2
3.0
3.0
4.0
SDOUT Output Logic High
SDOUT Output Logic Low
PHASE-LOCK ED LOOP NOMINAL
CENT ER FREQUENCY
CAPT URE RANGE
T RACK ING RANGE
ST AT IC PHASE ERROR (See Figure 7)
SET UP T IME (t
SU
)
HOLD T IME (t
H
)
PHASE DRIFT
JIT T ER
0.4
622.08
MHz
MHz
MHz
Degrees
ps
ps
Degrees
Degrees rms
Degrees rms
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
Unit Intervals
620
620
624
624
81
900
1050
50
3.6
3.6
2
7
–1 PRN Sequence
Figure 2
Figure 2
240 Bits, No T ransitions
2
7
–1 PRN Sequence
2
23
–1 PRN Sequence
f = 30 Hz
f = 300 Hz
f = 25 kHz
f = 250 kHz
f = 5 MHz
22
550
700
2.5
2.5
3000
300
3.7
0.56
0.45
JIT T ER T OLERANCE
24
1.7
0.28
0.18
JIT T ER T RANSFER
Peaking (Figure 14)
Bandwidth
Acquisition T ime
C
D
= 0.1
μ
F
C
D
= 0.47
μ
F
POWER SUPPLY VOLT AGE
POWER SUPPLY CURRENT
C
D
= 0.47
μ
F
0.04
333
dB
kHz
450
2
23
–1 PRN Sequence, T
A
= +25
°
C
V
CC
= 5 V, V
EE
= GND
V
MIN
to V
MAX
V
CC
= 5.0 V, V
EE
= GND,
T
A
= +25
°
C
2
×
10
6
8
×
10
6
3
×
10
6
12
×
10
6
5.5
Bit Periods
Bit Periods
Volts
4.5
55
80
100
mA
PECL OUT PUT VOLT AGE LEVELS
Output Logic High, V
OH
Output Logic Low, V
OL
SYMMET RY (Duty Cycle)
Recovered Clock Output, Pin 5
OUT PUT RISE / FALL T IMES
Rise T ime (t
R
)
Fall T ime (t
F
)
CLOCK SK EW (t
RCS
)
T
A
= +25
°
C
Referenced to V
CC
ρ
= 1/2, T
A
= +25
°
C,
V
CC
= 5 V, V
EE
= GND
–1.2
–2.2
–1.0
–2.0
–0.7
–1.7
Volts
Volts
45
55
%
20%–80%
80%–20%
Positive Number Indicates Clock
Leading Data
174
136
350
315
500
500
ps
ps
–100
130
250
ps
Specifications subject to change without notice.
(T
A
= T
MN
to T
MAX
, V
S
= V
MN
to V
MAX
, C
D
= 0.47
m
F, unless otherwse noted)
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