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參數資料
| 型號： | AD7889 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit 600 kSPS ADC(單電源600kSPS12位A/D轉換器) |
| 中文描述： | 12位600 ksps模數轉換器（單電源600kSPS12位的A / D轉換器） |
| 文件頁數： | 8/12頁 |
| 文件大小： | 285K |
| 代理商： | AD7889 |
AD7889
8
REV. B PRELIM. 7/97
Preliminary Technical Information
CIRCUIT DESCRIPTION
The AD7889 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, reference, A/D
converter and versatile interface logic functions on a single
chip. The signal scaling on the AD7889-1 allows the part to
handle either ±5V or ±10V input signals while operating
from a single +5V supply. The AD7889-2 handles either a
0 V to +2.5 V or 0 V to +5.0 V analog input range, while signal
scaling on the AD7889-3 allows it to handle ±2.5V input sig-
nals when operating from a single supply. The part requires a
+2.5V reference which can be provided from the parts own in-
ternal reference or from an external reference source.
Conversion is initiated on the AD7889 by pulsing the
CONVST
input. On the rising edge of
CONVST
, the track/
hold goes from track mode to hold mode and the conversion
sequence is started. At the end of conversion , the track/hold
returns to tracking mode and the acquisition time begins. Con-
version times for the part are 1.4μs(Mode A) and 1.6 μs
(Modes B-D) The track/hold acquisition time is 300ns. This al-
lows the AD7889 to operate at throughput rates up to
600kSPS.
Track/Hold Section
The track/hold amplifier on the AD7889 allows the ADC to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate of 600kHz (i.e., the
track/hold can handle input frequencies in excess of 300kHz).
The track/hold amplifier acquires an input signal to 12-bit ac-
curacy in less than 300ns. The operation of the track/hold
is essentially transparent to the user. The track/hold amplifier
goes from its tracking mode to its hold mode on the rising edge
of
CONVST
. The aperture time for the track/hold (i.e., the
delay time between the external
CONVST
signal and the
track/hold actually going into hold) is typically 15ns. At the
end of conversion, the part returns to its tracking mode. The
acquisition time of the track/hold amplifier begins at this point.
Reference Section
The AD7889 contains a single reference pin, labelled VREF,
which either provides access to the parts own +2.5V refer-
ence or to which an external +2.5V reference can be con-
nected to provide the reference source for the part. The part is
specified with a +2.5V reference voltage. Errors in the refer-
ence source will result in gain errors in the AD7889s transfer
function and will add to the specified full-scale errors on the
part. On the AD7889-1 and AD7889-3, it will also result in an
offset error injected in the attenuator stage.
The AD7889 contains an on-chip +2.5V reference. To use
this reference as the reference source for the AD7889, simply
connect a 0.1μF disc ceramic capacitor from the VREF pin to
AGND. The voltage that appears at this pin is internally buff-
ered before being applied to the ADC. If this reference is re-
quired for use external to the AD7889, it should be buffered as
the part has a FET switch in series with the reference output
resulting in a source impedance for this output of 5.5k
nominal. The tolerance on the internal reference is ±10mV at
25°C with a typical temperature coefficient of 25ppm/°C and
a maximum error over temperature of ±25mV.
If the application requires a reference with a tighter tolerance
or the AD7889 needs to be used with a system reference, then
the user has the option of connecting an external reference to
this VREF pin. The external reference will effectively overdrive
the internal reference and thus provide the reference source for
the ADC. The reference input is buffered before being ap-
plied to the ADC with the maximum input current is
±100μA. Suitable reference sources for the AD7889 include
the AD680, AD780 and REF43 precision +2.5V references.
INTERFACING
The part has a versatile serial 3 wire interface with four modes
of operation. The modes are selected using the CONTCLK
and 16/14B pins.
The serial interface can be set up to use either a
continuous or burst clock. With CONTCLK at a logic 1 the
AD7889 expects a continuous serial clock to be provided. With
CONTCLK at a logic 0 the AD7889 expects a burst serial clock to
be provided. Table I shows the interface modes available.
Table I. AD7889 Interface Modes
Interface
Mode
16/14B
CONTCLK
Mode A
Mode B
Mode C
Mode D
0
0
1
1
0
1
0
1
Figures 2a-2d show the timing diagrams for reading from the
AD7889 in the various serial interface modes.
RFS
is driven
low as the AD7889 outputs the data.
MODE A Description.
The AD7889 can be used in Mode A by connecting
CONTCLK and 16/14B to logic 0. In this mode the AD7889
provides a burst SCLK. The conversion is initiated by pulsing
CONVST.
14 SCLK pulses are provided to output the conver-
sion result. After the first two rising edges of SLCK (assuming
IDLEHI = 1) the
RFS
signal is asserted. The conversion result
is available on the next 12 falling SCLK edges.
MODE B Description.
The AD7889 can be used in Mode B by connecting
CONTCLK to logic 1 and 16/14B to logic 0. In this mode the
AD7889 expects a continuous SCLK to be provided.The con-
version is initiated by pulsing
CONVST.
The
RFS
signal is as-
serted after the first rising edge of the SCLK following a
CONVST
.The following 14 clock cycles contain the conver-
sion result with the first two bits being don't cares.The 15th
rising edge after the
CONVST
will bring the
RFS
back high.
MODE C Description.
The AD7889 can be used in Mode C by connecting
CONTCLK to logic 0 and 16/14B to logic 1. In this mode the
AD7889 expects a burst SCLK to be provided.The conversion
is initiated by pulsing
CONVST.
The
RFS
signal is then as-
serted and 16 serial clocks should be provided. The conversion
result will be valid on the falling edges of the 16 clock cycles
(assuming IDLEHI = 1 ). When the clock returns to its idle
state (dependent on IDLEHI) the
RFS
will return high.
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