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參數資料
| 型號： | AD7870A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete, 12-Bit, 100 kHz , Sampling ADC(完備的,頻率為100kHz,12位A/D轉換器) |
| 中文描述： | 完整的，12位，100千赫采樣ADC（完備的，頻率為100kHz的12位的A / D轉換器） |
| 文件頁數： | 5/12頁 |
| 文件大小： | 263K |
| 代理商： | AD7870A |
AD7870A
–5–
REV. 0
PIN DESCRIPTION
Pin
No.
Pin
Mnemonic
Function
1
2
3
RD
INT
CLK
Read. Active low logic input. This input is used in conjunction with
CS
low to enable the data outputs.
Interrupt, Active low logic output indicating converter status. See timing diagrams.
Clock input. An external TTL-compatible clock may be applied to this input pin. Alternatively, tying
this pin to V
SS
enables the internal laser-trimmed clock oscillator.
Data Bit 11 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the
12/
8
/CLK input (see below). When 12-bit parallel data is selected, this pin provides the DB11 output.
When byte data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus
interfacing. When HBEN is low, DB7/LOW to DB0/DB8 become DB7 to DB0. With HBEN high,
DB7/LOW to DB0/DB8 are used for the upper byte of data (see Table I).
Data Bit 10/Serial Strobe. When 12-bit parallel data is selected, this pin provides the DB10 output.
SSTRB
is an active low open-drain output that provides a strobe or framing pulse for serial data. An
external 4.7 k
pull-up resistor is required on
SSTRB
.
Data Bit 9/Serial Clock. When 12-bit parallel data is selected, this pin provides the DB9 output. SCLK is
the gated serial clock output derived from the internal or external ADC clock. If the 12/
8
/CLK input is at
–5 V, then SCLK runs continuously. If 12/
8
/CLK is at 0 V, then SCLK is gated off after serial
transmission is complete. SCLK is an open-drain output and requires an external 2 k
pull-up resistor.
Data Bit 8/Serial Data. When 12-bit parallel data is selected, this pin provides the DB8 output. SDATA
is an open-drain serial data output which is used with SCLK and
SSTRB
for serial data transfer. Serial
data is valid on the falling edge of SCLK while
SSTRB
is low. An external 4.7 k
pull-up resistor is
required on SDATA.
Three-state data outputs controlled by
CS
and
RD
. Their function depends on the 12/
8
/CLK
and HBEN inputs. With 12/
8
/CLK high, they are always DB7–DB4. With 12/
8
/CLK low or –5 V, their
function is controlled by HBEN (see Table I).
Digital Ground. Ground reference for digital circuitry.
Three-state data outputs which are controlled by
CS
and
RD
. Their function depends on the 12/8/CLK
and HBEN inputs. With/12/
8
/CLK high, they are always DB3–DB0. With 12/
8
/CLK low or –5 V, their
function is controlled by HBEN (see Table I).
Positive Supply, +5 V
±
5%.
Analog Ground. Ground reference for track/hold, reference and DAC.
Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability
is 500
μ
A.
Analog Input. The analog input range is
±
3 V.
Negative Supply, –5 V
±
5%.
Three Function Input. Defines the data format and serial clock format. With this pin at +5 V, the
output data format is 12-bit parallel only. With this pin at 0 V, either byte or serial data is available and SCLK
is not continuous. With this pin at –5 V, either byte or serial data is again available but SCLK is now
continuous.
Convert Start. A high to low transition on this input puts the track/hold into its hold mode and starts
conversion. This input is asynchronous to the CLK and independent of
CS
and
RD
.
Chip Select. Active low logic input. The device is selected when this input is active.
4
DB11/HBEN
5
DB10/
SSTRB
6
DB9/SCLK
7
DB8/SDATA
8–11
DB7/LOW–
DB4/LOW
12
13-16 DB3/DB11–
DB0/DB8
DGND
17
18
19
V
DD
AGND
REF OUT
20
21
22
V
IN
V
SS
12/
8
/CLK
23
CONVST
24
CS
Table I. Output Data for Byte Interfacing
HBEN
DB7/LOW
DB6/LOW
DB5/LOW
DB4/LOW
DB3/DB11
DB2/DB10
DB1/DB9
DB0/DB8
HIGH
LOW
LOW
LOW
LOW
DB11 (MSB) DB10
DB9
DB8
LOW
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
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