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參數資料
| 型號： | 62LV1024SC |
| 廠商： | BRILLIANCE SEMICONDUCTOR, INC. |
| 元件分類： | SRAM |
| 英文描述： | Very Low Power/Voltage CMOS SRAM 128K X 8 bit |
| 中文描述： | 非常低功率/電壓CMOS SRAM的128K的× 8位 |
| 文件頁數： | 4/11頁 |
| 文件大小： | 383K |
| 代理商： | 62LV1024SC |
Revision 2.2
April 2001
4
R0201-BS62LV1024
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
E1LQV
t
E2HOV
t
GLQV
t
E1LQX
t
E2HOX
t
GLQX
t
E1HQZ
t
E2HQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
DESCRIPTION
BS62LV1024-70
MIN. TYP. MAX.
UNIT
Read Cycle Time
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
t
OH
70
--
--
ns
Address Access Time
--
--
70
ns
Chip Select Access Time
(CE1)
--
--
70
ns
Chip Select Access Time
(CE2)
--
--
70
ns
Output Enable to Output Valid
--
--
50
ns
Chip Select to Output Low Z
(CE1)
10
--
--
ns
Chip Select to Output Low Z
(CE2)
10
--
--
ns
Output Enable to Output in Low Z
10
--
--
ns
Chip Deselect to Output in High Z
(CE1)
0
--
40
ns
Chip Deselect to Output in High Z
(CE2)
0
40
Output Disable to Output in High Z
0
--
35
ns
Output Disable to Address Change
10
--
--
ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS
( TA = 0
o
C to + 70
o
C, Vcc=3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E:
E
CHANGE :
STATE
UNKNOWN
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
BSI
BS62LV1024
667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10%
90%
←
Vcc
GND
→
←
5ns
90%
10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
1269
1404
5PF
FIGURE 1B
3.3V
INCLUDING
JIG AND
SCOPE
1269
100PF
FIGURE 1A
1404
OUTPUT
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